The present invention relates in general to communication systems, and is particularly directed to a bit error rate test (BERT) system, that is programmably configurable to emulate one or more independent BERT generators and thereby produce a sequence of test frames. The test frames contain test pattern codes associated with respectively different time division multiplexed (TDM) digital communication channels that are not necessarily mutually contiguous within a plurality of TDM timeslots of a network communication frame serving digital communication circuits. The programmable BERT system of the invention is operative to selectively interface the sequence of test frames with digital communication units of a channel bank over a serial network interface and to measure thereover the performance of the digital communication units.
The parameters of signals generated by digital communication equipments that interface with existing telecommunication networks are required to conform with prescribed industry (e.g., ANSI) standards. For example, a standard T1 data frame (having a data transport rate of 1.544 Mbps) contains 193 bits, including a framing bit and 192 channel bits. The channel bits may be undivided (non-channelized), or may be xe2x80x98channelizedxe2x80x99, by being subdivided into one or more timeslots or channels of some number of bits per channel, such as twenty-four basic rate (DS0) channels of eight bits each, as diagrammatically illustrated in FIG. 1. As shown in FIG. 2, when employed for the transport of integrated services digital network (ISDN) channels, these twenty-four basic rate DS0 channels (DS0-0, . . . , DS0-23) may be grouped in pairs of B1 and B2 bearer channels of eight bits each, and auxiliary (D and M) control channels associated with each pair of bearer channels.
A conventional (non-channelized) T1 BERT device typically generates a single stream of 192 bits that are is inserted sequentially across the entire frame of data. As long as the T1 circuit under test is non-channelized, such as a high data rate digital subscriber line (HDSL) or a fractional T1 loop, this standard T1 BERT device may be used, since all of the bits transmitted over the T1 interface are delivered to only one circuit under test and therefore will be returned from that circuit in the order transmitted. However, if the T1 circuit to be tested is channelized, such as one that is subdivided into channel units of a multi-unit channel bank, diagrammatically illustrated at 10 in FIG. 3, a conventional BERT device 12 cannot be used to test the circuit via the T1 network interface 14, since the channels of the channel units 16 of the channel bank 10 cannot be assumed to be xe2x80x98time sequence synchronousxe2x80x99.
More particularly, FIG. 4 shows a series of T1 test frames Frame 0, Frame 1, Frame 2, . . . , each of which is comprised of a sequence of twenty-four test pattern codes Ax, Bx, . . . AAx (where x is the-frame number), as asserted onto the T1 network interface 14 by the conventional non-channelized BERT device 12. Each channel unit 16 in the channel bank 10 transmits its (single) associated byte in a respective test frame received from the BERT out its transmit port, which is then immediately looped back to its receive port, and returned over the T1 network interface to the BERT device.
In an ideal world, each channel unit operates with zero latency, so that the bits of each successive test frame sourced from the BERT device will be received in exactly the same order as they are transmitted, enabling test frame pattern sync to be readily achieved in the BERT device""s receiver. In the real world, however, the respective channel units of the channel bank 10 exhibit different degrees of latency. As a consequence, frames returned to the BERT device have bytes from some DS0s that are shifted in time, as shown diagrammatically in the non-limiting test frame sequence example of FIG. 5. This means that the frames returned from the channel bank will not match the transmitted test frames, preventing the BERT device from achieving pattern sync.
To test a channelized T1 network, therefore, a channelized BERT device, namely, one which is operative to test one channel at a time, must be employed. This individual testing of only one of the bank""s (twenty-four) channel units is shown diagrammatically in FIG. 6, wherein each test frame of the test frame sequence Frame 0, Frame 1, Frame 2, . . . contains only a single test code (B0, B1, B2, . . . ) associated with only a single selected channel (timeslot DS0-1). As further shown in FIG. 7, although the channel unit under test returns the transmitted test frames with a two frame latency, that delay poses no problem, since the bytes of the returned test pattern frames are received in exactly the same order as they are transmitted. However, a major shortcoming in testing channelized networks in this manner is the considerable time required to test all of the channels.
In addition to being unable to test a xe2x80x98channelizedxe2x80x99 network, a conventional BERT device is also unable to test non-contiguous and non-adjacent channels, such as a frame of basic rate 3-DS0 ISDN channels, shown diagrammatically in FIG. 2 referenced above, or the frame of BR1/10 bits of a ten channel ISDN frame shown in FIG. 8, and described in U.S. Pat. No. 5,771,236, issued Jun. 23, 1998 to Sansom et al (hereinafter referred to as the ""236 patent), entitled xe2x80x9cMethod for Increasing ISDN Channel Capacity of TDM Serial Communication Link for Digital Subscriber Line Channels,xe2x80x9d assigned to the assignee of the present application and the disclosure of which is incorporated herein. The main problem in testing a non-adjacent channel configured ISDN frame is the fact that the (D/M) data within the auxiliary control channels is no longer contiguous with that in the adjacent bearer channels, due to the presence of interleaved bits. A conventional BERT device cannot xe2x80x98skipxe2x80x99bits. Similarly, the D channels of a BR1/10 ISDN frame occupy multiple DS0 channels that are non-contiguous with their associated bearer channels. Since the data within a channel is no longer contiguous, and is not transferred across adjacent DS0s, a conventional BERT device cannot be used to test across the network interface. Instead, as diagrammatically illustrated in FIG. 9, a separate single channel BERT device is required to test each channel, increasing the number and cost of system resources.
In accordance with the present invention, the shortcomings of conventional BERT schemes, such as those described above, are effectively obviated by a new and improved bit error rate test system that is programmably configurable to emulate one or more independent BERT generators that generate channel pattern test codes for testing one or more channels of a telecommunication channel bank. In effect, the channel pattern test codes generated by the programmably configurable BERT generator of the present invention may be considered to be xe2x80x98pseudoxe2x80x99subscriber channelsxe2x80x94conveying test pattern codes, as the effective functionality of the output codes generated by the BERT generator is to test the channels, rather than deliver information signals via the channels to circuits served by associated channel units.
For this purpose, a data channel-specific BERT generator unit is programmed to implement one or more individual BERT pattern generators, depending upon the type or format of channelization of the circuits under test. Each BERT pattern generator generates a respective test code pattern that is used to form successive test frames for testing one or more data channels. The BERT test patterns are coupled to a data channel-specific network test frame buffer, which is programmably configurable under software control to provide plural channel registers that store an entire test frame for transmission to the channel circuits or units under test.
The input/output addressing scheme for the test frame buffer is programmed to logically map grouped data channel bits into physical bit positions within an outgoing test frame. Although the bits stored in the registers of the frame buffer have a one-to-one relationship with the bits in the outgoing network test frame, the data channels need not be in any specific order within the network test frame buffer. The test pattern codes stored in the sub-channel registers of the test frame buffer are controllably assembled into a test frame by a data channel-specific control logic unit, which controls the placing of a test data channel generated by the BERT generator unit into the network frame buffer as well as its extraction from a bit stream returned from the network. The contents of the data channel-specific registers of the network frame buffer are serially clocked through a transmit shift register into an external network framer under the control of a transmit data channel controller. Transmission frame synchronization is controlled from the external network framer.
On the receive side of the network interface, the incoming network signal is converted into a serial bit stream and, along with a received frame synchronization signal used to identify the beginning of the frame, is fed by the external framer into a receive shift register. The contents of the receive shift register are selectively demultiplexed into a data channel-specific virtual receiver array that is programmed to implement one or more pattern receivers, depending on the number of sub-channels within the data channel, and functions as a virtual array of independent BERT receivers, one per data channel.
A receive data channel controller monitors the reassembly of the recovered sub-channels out of the received serial bit stream and controls the assembly of sub-channels from the incoming serial bit stream, the processing of these bits through the virtual receiver array, and the storing of error counts and state information in memory. The receive data channel controller essentially operates as a counter that counts from one up to the number of data channels present within the frame. It receives its timing from the external framer, so that it can properly extract data from each network frame.
When all the bits of a particular channel are available, the data channel-specific BERT receiver recalls state information stored in a data channel memory for the data channel being processed. To check for bit errors in the frame sequence, the data channel bits stored in the BERT receiver registers are fed serially into associated pattern comparators and compared with the test pattern codes produced by the transmit BERT generator. Any bit errors are accumulated in associated registers of the memory under the control of the receive data channel controller as the processing of each data channel is completed. Once all the bits of a respective data channel have been processed, the state of that channel is saved in its associated state memory. The cycle repeats for the next data channel until all data channels within the frame have been processed.